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<!DOCTYPE html>
<html>
<head>
<meta charset="utf-8">
<meta name="viewport" content="width=device-width, initial-scale=1">
<style type="text/css">
@import url('../css/main.css');
</style>
<title>ASUS KFSN4-DRE server/workstation board</title>
</head>
<body>
<div class="section">
<h1 id="pagetop">ASUS KFSN4-DRE server/workstation board</h1>
<p>
This is a server board using AMD hardware (Fam10h). It can also be used
for building a high-powered workstation. Powered by libreboot.
</p>
<p>
<b>
NOTE: This board is unsupported in libreboot 20150518.
To use it in libreboot, for now, you must build for it
from source using the libreboot git repository.
</b>
</p>
<p>
Flashing instructions can be found at <a href="../install/index.html#flashrom">../install/index.html#flashrom</a>
</p>
<p>
<a href="index.html">Back to previous index</a>.
</p>
</div>
<div class="section">
<h1 id="formfactor">Form factor</h1>
<p>
These boards use the SSI EEB 3.61 form factor; make sure
that your case supports this. This form factor is similar
to E-ATX in that the size is identical, but the position of
the screws are different.
</p>
</div>
<div class="section">
<h1 id="flashchips">Flash chips</h1>
<p>
These boards use LPC flash (not SPI), in a PLCC socket. The default flash size
1MiB (8Mbits), and can be upgraded to 2MiB (16Mbits).
SST49LF080A is the default that the board uses.
SST49LF016C is an example of a 2MiB (16Mbits) chip, which might work.
It is believed that 2MiB (16Mbits) is the maximum size available for the flash chip.
</p>
<p>
<b>
DO NOT hot-swap the chip with your bare hands. Use a PLCC
chip extractor. These can be found online.
</b>
</p>
</div>
<div class="section">
<h1 id="graphics">Native graphics initialization</h1>
<p>
Native graphics initialization exists (XGI Z9s) for this board.
Framebuffer- and text-mode both work. A serial port is also
available.
</p>
</div>
<div class="section">
<h1>Memory</h1>
<p>
DDR2 533/667 Registered ECC. 16 slots. Total capacity up to 64GiB.
</p>
</div>
<div class="section">
<h1 id="hexcore">Hex-core CPUs</h1>
<p>
PCB revision 1.05G is the best version of this board (the
revision number will be printed on the board), because it
can use dual hex-core CPUs (Opteron 2400/8400 series). Other
revisions are believed to only support dual quad-core CPUs.
</p>
</div>
<div class="section">
<h1 id="issues">Current issues</h1>
<ul>
<li>
There seems to be a 30 second bootblock delay (observed by tpearson);
the system otherwise boots and works as expected.
See <a href="text/kfsn4-dre/bootlog.txt">text/kfsn4-dre/bootlog.txt</a>
- this uses the 'simple' bootblock, while tpearson uses the 'normal'
bootblock, which tpearson suspects may be a possible cause.
He says that he will look into it.
<a href="http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asus/kfsn4-dre/4.0-10101-g039edeb/2015-06-27T03:59:16Z/config.txt;h=4742905c185a93fbda8eb14322dd82c70641aef0;hb=055f5df4e000a97453dfad6c91c2d06ea22b8545">This config</a> doesn't have the issue.
</li>
<li>
Text-mode is a bit jittery (but still usable). (the jitter disappears
if using KMS, once the kernel starts. The jitter will remain, if
booting the kernel in text-mode).
</li>
</ul>
</div>
<div class="section">
<h1>Other information</h1>
<p>
<a href="ftp://ftp.sgi.com/public/Technical%20Support/Pdf%20files/Asus/kfsn4-dre.pdf">specifications</a>
</p>
</div>
<div class="section">
<p>
Copyright © 2015 Francis Rowe <info@gluglug.org.uk><br/>
This document is released under the Creative Commons Attribution-ShareAlike 4.0 International Public License and all future versions.
A copy of the license can be found at <a href="../cc-by-sa-4.txt">../cc-by-sa-4.txt</a>.
</p>
<p>
This document is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See <a href="../cc-by-sa-4.txt">../cc-by-sa-4.txt</a> for more information.
</p>
</div>
</body>
</html>
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