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diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 4dd2ccf..5dbaff3 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -33,6 +33,8 @@
#define GDRST 0xc0
+#define BSM 0x5c
+
#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8)
#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4)
#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2)
@@ -51,11 +53,19 @@
static int gtt_setup(unsigned int mmiobase)
{
unsigned long PGETBL_save;
-
- PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
+ unsigned long tom; // top of memory
+
+ /*
+ * The Video BIOS places the GTT right below top of memory.
+ * It is not documented in the Intel 945 datasheet, but the Intel
+ * developers said that it is normally placed there.
+ *
+ * TODO: Add option to make the GTT size runtime
+ * configurable
+ */
+ tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24;
+ PGETBL_save = tom - 256 * KiB;
PGETBL_save |= PGETBL_ENABLED;
-
- PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000;
PGETBL_save |= 2; /* set GTT to 256kb */
write32(mmiobase + GFX_FLSH_CNTL, 0);
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