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From b4e60bb51855c3edb3c41fbe7f6378a638df9a95 Mon Sep 17 00:00:00 2001
From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
Date: Sat, 5 Sep 2015 18:46:54 -0500
Subject: [PATCH 018/146] cpu/amd/model_10xxx: Clean up debugging statements
---
src/cpu/amd/model_10xxx/fidvid.c | 43 +++++++++++++++++++-------------------
1 file changed, 21 insertions(+), 22 deletions(-)
diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index 36bdf36..99ffcc8 100644
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -460,35 +461,35 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
/* check PVI/SVI */
- u32 dword = pci_read_config32(dev, 0xA0);
+ u32 dword = pci_read_config32(dev, 0xa0);
- /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */
- /* PllLockTime and PsiVidEn set in ruleset in defaults.h */
+ /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */
+ /* PllLockTime and PsiVidEn set in ruleset in defaults.h */
if (dword & PVI_MODE) { /* PVI */
/* set slamVidMode to 0 for PVI */
dword &= VID_SLAM_OFF ;
} else { /* SVI */
/* set slamVidMode to 1 for SVI */
dword |= VID_SLAM_ON;
- }
+ }
/* set the rest of A0 since we're at it... */
- if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) {
- dword |= NB_PSTATE_FORCE_ON;
+ if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) {
+ dword |= NB_PSTATE_FORCE_ON;
} // else should we clear it ?
if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) {
- dword |= BP_INS_TRI_EN_ON ;
+ dword |= BP_INS_TRI_EN_ON ;
}
/* TODO: look into C1E state and F3xA0[IdleExitEn]*/
#if CONFIG_SVI_HIGH_FREQ
- if (cpuRev & AMD_FAM10_C3) {
- dword |= SVI_HIGH_FREQ_ON;
- }
- #endif
- pci_write_config32(dev, 0xA0, dword);
+ if (cpuRev & AMD_FAM10_C3) {
+ dword |= SVI_HIGH_FREQ_ON;
+ }
+ #endif
+ pci_write_config32(dev, 0xa0, dword);
}
static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
@@ -581,7 +582,7 @@ static void prep_fid_change(void)
nodes = get_nodes();
for (i = 0; i < nodes; i++) {
- printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
+ printk(BIOS_DEBUG, "Prep FID/VID Node:%02x\n", i);
dev = NODE_PCI(i, 3);
u32 cpuRev = mctGetLogicalCPUID(0xFF) ;
u8 procPkg = mctGetProcessorPackageType();
@@ -591,25 +592,23 @@ static void prep_fid_change(void)
/* Figure out the value for VsSlamTime and program it */
recalculateVsSlamTimeSettingOnCorePre(dev);
- config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
+ config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
config_power_ctrl_misc_reg(dev,cpuRev,procPkg);
config_nb_syn_ptr_adj(dev,cpuRev);
- config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg);
+ config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg);
dword = pci_read_config32(dev, 0x80);
- printk(BIOS_DEBUG, " F3x80: %08x \n", dword);
+ printk(BIOS_DEBUG, " F3x80: %08x\n", dword);
dword = pci_read_config32(dev, 0x84);
- printk(BIOS_DEBUG, " F3x84: %08x \n", dword);
+ printk(BIOS_DEBUG, " F3x84: %08x\n", dword);
dword = pci_read_config32(dev, 0xD4);
- printk(BIOS_DEBUG, " F3xD4: %08x \n", dword);
+ printk(BIOS_DEBUG, " F3xD4: %08x\n", dword);
dword = pci_read_config32(dev, 0xD8);
- printk(BIOS_DEBUG, " F3xD8: %08x \n", dword);
+ printk(BIOS_DEBUG, " F3xD8: %08x\n", dword);
dword = pci_read_config32(dev, 0xDC);
- printk(BIOS_DEBUG, " F3xDC: %08x \n", dword);
-
-
+ printk(BIOS_DEBUG, " F3xDC: %08x\n", dword);
}
}
--
1.7.9.5
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