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From 77935659fbe9426e7a65ecc5506beb4491171e7f Mon Sep 17 00:00:00 2001
From: Timothy Pearson <tpearson@raptorengineeringinc.com>
Date: Fri, 26 Jun 2015 17:49:25 -0500
Subject: [PATCH 079/143] northbridge/amd/amdmct/mct_ddr3: Set SkewMemClk when
both DCTs are in use
Change-Id: Ibcce54fc53b79beba2f790994bcf87cc0354213a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
---
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 41 +++++++++++++++++++++------
src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 +-
2 files changed, 34 insertions(+), 9 deletions(-)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index bb5593d..f3d5cb8 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -2645,7 +2645,7 @@ static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC
/* Reset DCT registers */
ClearDCT_D(pMCTstat, pDCTstat, dct);
- pDCTstat->stopDCT = 1; /*preload flag with 'disable' */
+ pDCTstat->stopDCT[dct] = 1; /* preload flag with 'disable' */
if (!is_fam15h()) {
/* Enable DDR3 support */
@@ -2656,7 +2656,7 @@ static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC
/* Read the SPD information into the data structures */
if (mct_DIMMPresence(pMCTstat, pDCTstat, dct) < SC_StopError) {
- printk(BIOS_DEBUG, "\t\tDCTInit_D: mct_DIMMPresence Done\n");
+ printk(BIOS_DEBUG, "\t\tDCTPreInit_D: mct_DIMMPresence Done\n");
}
}
@@ -2682,17 +2682,40 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst
printk(BIOS_DEBUG, "\t\tDCTInit_D: AutoConfig_D Done\n");
if (PlatformSpec_D(pMCTstat, pDCTstat, dct) < SC_StopError) {
printk(BIOS_DEBUG, "\t\tDCTInit_D: PlatformSpec_D Done\n");
- pDCTstat->stopDCT = 0;
- if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW))) {
- printk(BIOS_DEBUG, "\t\tDCTInit_D: StartupDCT_D\n");
- StartupDCT_D(pMCTstat, pDCTstat, dct); /*yeaahhh! */
- }
+ pDCTstat->stopDCT[dct] = 0;
}
}
}
}
- if (pDCTstat->stopDCT) {
+
+}
+
+static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct)
+{
+ uint32_t dword;
+
+ /* Finalize DRAM init on a single node */
+ if (is_fam15h()) {
+ /* Set memory clock skew if needed */
+ if (dct == 0) {
+ if (!pDCTstat->stopDCT[0] && !pDCTstat->stopDCT[1]) {
+ dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, 0x98, 0x0d0fe00a);
+ dword |= (0x1 << 4); /* SkewMemClk = 1 */
+ Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, 0x98, 0x0d0fe00a, dword);
+ }
+ }
+ }
+
+ if (!pDCTstat->stopDCT[dct]) {
+ if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW))) {
+ printk(BIOS_DEBUG, "\t\tDCTFinalInit_D: StartupDCT_D Start\n");
+ StartupDCT_D(pMCTstat, pDCTstat, dct);
+ printk(BIOS_DEBUG, "\t\tDCTFinalInit_D: StartupDCT_D Done\n");
+ }
+ }
+
+ if (pDCTstat->stopDCT[dct]) {
dword = 1 << DisDramInterface;
Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x94, dword);
@@ -4350,6 +4373,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
/* Config. DCT0 for Ganged or unganged mode */
DCTInit_D(pMCTstat, pDCTstat, 0);
+ DCTFinalInit_D(pMCTstat, pDCTstat, 0);
if (pDCTstat->ErrCode == SC_FatalErr) {
/* Do nothing goto exitDCTInit; any fatal errors? */
} else {
@@ -4359,6 +4383,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
err_code = pDCTstat->ErrCode; /* save DCT0 errors */
pDCTstat->ErrCode = 0;
DCTInit_D(pMCTstat, pDCTstat, 1);
+ DCTFinalInit_D(pMCTstat, pDCTstat, 1);
if (pDCTstat->ErrCode == 2) /* DCT1 is not Running */
pDCTstat->ErrCode = err_code; /* Using DCT0 Error code to update pDCTstat.ErrCode */
} else {
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index 8c9da47..7bc392b 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -338,7 +338,7 @@ struct DCTStatStruc { /* A per Node structure*/
u8 Node_ID; /* Node ID of current controller */
uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */
uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */
- uint8_t stopDCT; /* Set if the DCT will be stopped */
+ uint8_t stopDCT[2]; /* Set if the DCT will be stopped */
u8 ErrCode; /* Current error condition of Node
0= no error
1= Variance Error, DCT is running but not in an optimal configuration.
--
1.7.9.5
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