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| author | Andrew Robbins <contact@andrewrobbins.info> | 2019-01-12 19:30:37 -0500 |
|---|---|---|
| committer | Andrew Robbins <contact@andrewrobbins.info> | 2019-01-12 19:30:37 -0500 |
| commit | f8cf9dd9488fc3f4ac1993459d05ef99a4e5ba0f (patch) | |
| tree | 996709748d5e34e7fdd09939ee3537e7b91f3135 /projects/coreboot | |
| parent | 86ba2c05413b7ea31c475ec7dccc7ec851cf0e8d (diff) | |
| download | librebootfr-f8cf9dd9488fc3f4ac1993459d05ef99a4e5ba0f.tar.gz librebootfr-f8cf9dd9488fc3f4ac1993459d05ef99a4e5ba0f.zip | |
Create 1MiB coreboot config/target for D945GCLF
Previously it was thought that only boards with 512KiB flash chips
were produced but JohnMH (in #libreboot) ran across one with an
SST25LF080A 1MiB flash.
D945GCLF Coreboot ROMs can be built with, e.g.:
'./libreboot build coreboot d945gclf textmode 1mb'
Diffstat (limited to 'projects/coreboot')
| -rw-r--r-- | projects/coreboot/configs/d945gclf/textmode/1mb/config | 5 | ||||
| -rw-r--r-- | projects/coreboot/configs/d945gclf/textmode/targets | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/projects/coreboot/configs/d945gclf/textmode/1mb/config b/projects/coreboot/configs/d945gclf/textmode/1mb/config new file mode 100644 index 00000000..020bc913 --- /dev/null +++ b/projects/coreboot/configs/d945gclf/textmode/1mb/config @@ -0,0 +1,5 @@ +CONFIG_CBFS_SIZE=0x100000 +CONFIG_COREBOOT_ROMSIZE_KB_512=n +CONFIG_COREBOOT_ROMSIZE_KB_1024=y +CONFIG_COREBOOT_ROMSIZE_KB=1024 +CONFIG_ROM_SIZE=0x100000 diff --git a/projects/coreboot/configs/d945gclf/textmode/targets b/projects/coreboot/configs/d945gclf/textmode/targets index c01fccf5..8f8c3862 100644 --- a/projects/coreboot/configs/d945gclf/textmode/targets +++ b/projects/coreboot/configs/d945gclf/textmode/targets @@ -1,2 +1,3 @@ 16mb +1mb 512kb |