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* Restructure KCMA-D8 coreboot target directoriesAndrew Robbins2019-01-1412-3/+4
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure GA-G41M-ES2L coreboot target directoriesAndrew Robbins2019-01-1425-15/+10
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure D945GCLF coreboot target directoriesAndrew Robbins2019-01-1415-0/+3
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure D510MO coreboot target directoriesAndrew Robbins2019-01-1412-3/+4
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Create SeaBIOS/GRUB targets for D945GCLF corebootAndrew Robbins2019-01-123-0/+4
| | | | | | | D945GCLF ROMs can now be built with either SeaBIOS or GRUB as a default payload for use with a 1MiB flash, e.g.: './libreboot build coreboot d945gclf textmode 1mb seabios'
* Create 1MiB coreboot config/target for D945GCLFAndrew Robbins2019-01-122-0/+6
| | | | | | | | | Previously it was thought that only boards with 512KiB flash chips were produced but JohnMH (in #libreboot) ran across one with an SST25LF080A 1MiB flash. D945GCLF Coreboot ROMs can be built with, e.g.: './libreboot build coreboot d945gclf textmode 1mb'
* Update coreboot patch removing git submodulesAndrew Robbins2018-12-071-21/+21
| | | | | Paul Kocialkowski was not retained as the original author due to the triviality of the patch.
* Bump coreboot revision to pull in buildgcc v1.53Andrew Robbins2018-12-071-1/+1
| | | | | | | The revision currently used has an issue building crossgcc due to a libelf bug. Upstream no longer depends on libelf when building crossgcc (since afda56e1ad8719a1) so using a more recent revision sidesteps this issue.
* Amend path to SeaBIOS payload in coreboot configsAndrew Robbins2018-11-2456-56/+56
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* Create SeaBIOS/GRUB targets for Z61t corebootAndrew Robbins2018-11-166-0/+8
| | | | | | | Z61t ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot z61t textmode 2mb seabios'
* Create 2,16MiB Coreboot configs/targets for Z61tAndrew Robbins2018-11-164-0/+12
| | | | | | | | | | | | | | 2MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Z61t Coreboot ROMs can be built with, e.g.: './libreboot build coreboot z61t textmode 2mb'
* Add Z61t coreboot targetAndrew Robbins2018-11-163-0/+676
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* Add iMac5,2 as MacBook2,1 variantAndrew Robbins2018-11-164-0/+9
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* Create Coreboot Depthcharge target for Veyron SpeedyAndrew Robbins2018-10-304-0/+4
| | | | | | | Veyron Speedy ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron speedy corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Veyron SpeedyAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Speedy Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron speedy corebootfb 4mb'
* Correct CBFS_SIZE in Veyron Speedy Coreboot ConfigAndrew Robbins2018-10-301-1/+1
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* Create Coreboot Depthcharge target for Veyron MinnieAndrew Robbins2018-10-304-0/+4
| | | | | | | Veyron Minnie ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron minnie corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Veyron MinnieAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Minnie Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron minnie corebootfb 4mb'
* Correct CBFS_SIZE in Veyron Minnie Coreboot ConfigAndrew Robbins2018-10-301-1/+1
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* Create Coreboot Depthcharge target for Veyron MickeyAndrew Robbins2018-10-302-0/+2
| | | | | | | Veyron Mickey ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron mickey corebootfb 4mb depthcharge'
* Create 4MiB Coreboot config/target for Veyron MickeyAndrew Robbins2018-10-303-0/+6
| | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is not included (yet) as I was unable to find a teardown of this device (Asus Chromebit CS10) online to be sure that reassembly is possible. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Mickey Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron mickey corebootfb 4mb'
* Create Coreboot Depthcharge target for Veyron JerryAndrew Robbins2018-10-304-0/+4
| | | | | | | Veyron Jerry ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron jerry corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Veyron JerryAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Jerry Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron jerry corebootfb 4mb'
* Correct CBFS_SIZE in Veyron Jerry Coreboot ConfigAndrew Robbins2018-10-301-1/+1
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* Create Coreboot Depthcharge target for Nyan BlazeAndrew Robbins2018-10-294-0/+4
| | | | | | | Nyan Blaze ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot nyan blaze corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Nyan BlazeAndrew Robbins2018-10-294-0/+12
| | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Nyan Blaze Coreboot ROMs can be built with, e.g.: './libreboot build coreboot nyan blaze corebootfb 4mb'
* Create Coreboot Depthcharge target for Nyan BigAndrew Robbins2018-10-294-0/+4
| | | | | | Nyan Big ROMs are built with Depthcharge as its default payload, e.g.: './libreboot build coreboot nyan big corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Nyan BigAndrew Robbins2018-10-294-0/+12
| | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Nyan Big Coreboot ROMs can be built with, e.g.: './libreboot build coreboot nyan big corebootfb 4mb'
* Enable additional options in Nyan Blaze configAndrew Robbins2018-10-251-2/+2
| | | | | | Options updated (with new values): CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" # CONFIG_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is not set
* Update Nyan Blaze Coreboot configAndrew Robbins2018-10-251-2/+726
| | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* Enable additional options in Nyan Big configAndrew Robbins2018-10-251-3/+3
| | | | | | | Options updated (with new values): CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
* Update Nyan Big Coreboot configAndrew Robbins2018-10-251-2/+731
| | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* Enable additional options in Veyron Mickey configAndrew Robbins2018-10-251-4/+4
| | | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
* Update Veyron Mickey Coreboot configAndrew Robbins2018-10-251-0/+710
| | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* Enable additional options in Veyron Jerry configAndrew Robbins2018-10-251-3/+3
| | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" # CONFIG_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is not set
* Update Veyron Jerry Coreboot configAndrew Robbins2018-10-251-2/+722
| | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* Enable additional options in Veyron Speedy configAndrew Robbins2018-10-251-4/+4
| | | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
* Update Veyron Speedy Coreboot configAndrew Robbins2018-10-251-2/+727
| | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* Enable additional options in Veyron Minnie configAndrew Robbins2018-10-251-4/+4
| | | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
* Update Veyron Minnie Coreboot configAndrew Robbins2018-10-251-2/+727
| | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* Create SeaBIOS/GRUB targets for D510MO CorebootAndrew Robbins2018-10-226-0/+8
| | | | | | | D510MO ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot d510mo textmode 1mb seabios'
* Create 1,16MiB Coreboot configs/targets for D510MOAndrew Robbins2018-10-224-0/+12
| | | | | | | | | | | | | | 1MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. D510MO Coreboot ROMs can be built with, e.g.: './libreboot build coreboot d510mo textmode 1mb'
* Create SeaBIOS/GRUB targets for D945GCLF CorebootAndrew Robbins2018-10-215-0/+6
| | | | | | | | | | | Due to the limited flash space on the board, SeaBIOS is currently the sole payload option when building 512KiB-sized ROMs. D945GCLF ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot d945gclf textmode 512kb seabios', or './libreboot build coreboot d945gclf textmode 16mb grub'
* Create 512KiB,16MiB Coreboot configs/targets for D945GCLFAndrew Robbins2018-10-213-0/+11
| | | | | | | | | | | | | | 512KiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. D945GCLF Coreboot ROMs can be built with, e.g.: './libreboot build coreboot d945gclf textmode 512kb'
* Create SeaBIOS/GRUB targets for GA-G41M-ES2L CorebootAndrew Robbins2018-10-2012-0/+16
| | | | | | | GA-G41M-ES2L ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot ga-g41m-es2l corebootfb 1mb seabios'
* Create 1,16MiB Coreboot configs/targets for GA-G41M-ES2LAndrew Robbins2018-10-206-0/+22
| | | | | | | | 1MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with larger flash chips. GA-G41M-ES2L Coreboot ROMs can be built with, e.g.: './libreboot build coreboot ga-g41m-es2l textmode 1mb'
* Create GA-G41M-ES2L corebootfb/textmode Coreboot targetsAndrew Robbins2018-10-203-0/+6
| | | | | | | | | | | | | | | The corebootfb ROM will use Coreboot's framebuffer for display while the textmode ROM will use the legacy VGA text mode which is necessary for payloads such as Memtest86+. Options (and their values) changed in the new corebootfb config: #CONFIG_VGA_TEXT_FRAMEBUFFER is not set CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y CONFIG_LINEAR_FRAMEBUFFER=y GA-G41M-ES2L Coreboot ROMs can now be built with './libreboot build coreboot ga-g41m-es2l corebootfb' or './libreboot build coreboot ga-g41m-es2l textmode', respectively.
* Create SeaBIOS/GRUB targets for KCMA-D8 CorebootAndrew Robbins2018-10-206-0/+8
| | | | | | | KCMA-D8 ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot kcma-d8 textmode 2mb seabios'
* Create 2mb,16mb Coreboot configs/targets for KCMA-D8Andrew Robbins2018-10-204-0/+12
| | | | | | | | | | Text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. KCMA-D8 Coreboot ROMs can be built with, e.g.: './libreboot build coreboot kcma-d8 textmode 2mb'
* Create SeaBIOS/GRUB targets for KFSN4-DRE CorebootAndrew Robbins2018-10-2012-0/+16
| | | | | | | KFSN4-DRE ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot kfsn4-dre textmode 2mb seabios'
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